From 0865e43e404aa17ea2a06e2183c812ca76bb78a5 Mon Sep 17 00:00:00 2001 From: Sergey Fedorov Date: Sat, 22 Nov 2025 20:34:28 +0700 Subject: [PATCH 1/7] AArch64: add missing Apple CPU names and use them by default Cherry-picks from https://github.com/llvm/llvm-project/commit/903e5c3028d61481c570c09eeb5e7a920c2d7d38 --- .../llvm/Support/AArch64TargetParser.def | 18 ++++ llvm/lib/Target/AArch64/AArch64.td | 101 +++++++++++++++++- llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 6 +- llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 +- .../Target/AArch64/AArch64SystemOperands.td | 2 +- 5 files changed, 127 insertions(+), 6 deletions(-) diff --git llvm/include/llvm/Support/AArch64TargetParser.def llvm/include/llvm/Support/AArch64TargetParser.def index 6772e5f9b73..4c5075fde2f 100644 --- llvm/include/llvm/Support/AArch64TargetParser.def +++ llvm/include/llvm/Support/AArch64TargetParser.def @@ -85,6 +85,24 @@ AARCH64_CPU_NAME("cortex-a75", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC)) AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_NONE)) +AARCH64_CPU_NAME("apple-a7", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_NONE)) +AARCH64_CPU_NAME("apple-a8", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_NONE)) +AARCH64_CPU_NAME("apple-a9", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_NONE)) +AARCH64_CPU_NAME("apple-a10", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_CRC | AArch64::AEK_RDM)) +AARCH64_CPU_NAME("apple-a11", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_NONE)) +AARCH64_CPU_NAME("apple-a12", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_FP16)) +AARCH64_CPU_NAME("apple-a13", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_FP16 | AArch64::AEK_FP16FML)) +AARCH64_CPU_NAME("apple-s4", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_FP16)) +AARCH64_CPU_NAME("apple-s5", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_FP16)) AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_CRC)) AARCH64_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, diff --git llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64.td index a69d38144c7..4f944c9f251 100644 --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -334,8 +334,8 @@ def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", // Note that cyclone does not fuse AES instructions, but newer apple chips do // perform the fusion and cyclone is used by default when targetting apple OSes. -def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", - "Cyclone", [ +def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", + "Apple A7 (the CPU formerly known as Cyclone)", [ FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, @@ -350,6 +350,83 @@ def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", FeatureZCZeroingFPWorkaround ]>; +def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", + "Apple A10", [ + FeatureAlternateSExtLoadCVTF32Pattern, + FeatureArithmeticBccFusion, + FeatureArithmeticCbzFusion, + FeatureCrypto, + FeatureDisableLatencySchedHeuristic, + FeatureFPARMv8, + FeatureFuseAES, + FeatureFuseCryptoEOR, + FeatureNEON, + FeaturePerfMon, + FeatureZCRegMove, + FeatureZCZeroing, + FeatureCRC, + FeatureRDM, + FeaturePAN, + FeatureLOR, + FeatureVH, + ]>; + +def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", + "Apple A11", [ + FeatureAlternateSExtLoadCVTF32Pattern, + FeatureArithmeticBccFusion, + FeatureArithmeticCbzFusion, + FeatureCrypto, + FeatureDisableLatencySchedHeuristic, + FeatureFPARMv8, + FeatureFuseAES, + FeatureFuseCryptoEOR, + FeatureNEON, + FeaturePerfMon, + FeatureZCRegMove, + FeatureZCZeroing, + FeatureFullFP16, + HasV8_2aOps + ]>; + +def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", + "Apple A12", [ + FeatureAlternateSExtLoadCVTF32Pattern, + FeatureArithmeticBccFusion, + FeatureArithmeticCbzFusion, + FeatureCrypto, + FeatureDisableLatencySchedHeuristic, + FeatureFPARMv8, + FeatureFuseAES, + FeatureFuseCryptoEOR, + FeatureNEON, + FeaturePerfMon, + FeatureZCRegMove, + FeatureZCZeroing, + FeatureFullFP16, + HasV8_3aOps + ]>; + +def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", + "Apple A13", [ + FeatureAlternateSExtLoadCVTF32Pattern, + FeatureArithmeticBccFusion, + FeatureArithmeticCbzFusion, + FeatureCrypto, + FeatureDisableLatencySchedHeuristic, + FeatureFPARMv8, + FeatureFuseAES, + FeatureFuseCryptoEOR, + FeatureNEON, + FeaturePerfMon, + FeatureZCRegMove, + FeatureZCZeroing, + FeatureFullFP16, + FeatureFP16FML, + FeatureSHA3, + HasV8_4aOps + ]>; + def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", "Samsung Exynos-M1 processors", [FeatureSlowPaired128, @@ -514,7 +591,6 @@ def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; -def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; @@ -530,6 +606,25 @@ def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; +// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. +def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>; + +// iPhone and iPad CPUs +def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>; +def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>; +def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>; +def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>; +def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>; +def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>; +def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>; + +// watch CPUs. +def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>; +def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>; + +// Alias for the latest Apple processor model supported by LLVM. +def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>; + //===----------------------------------------------------------------------===// // Assembly parser //===----------------------------------------------------------------------===// diff --git llvm/lib/Target/AArch64/AArch64Subtarget.cpp llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 04bb90d30d6..57d58882cd2 100644 --- llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -67,7 +67,11 @@ void AArch64Subtarget::initializeProperties() { // this in the future so we can specify it together with the subtarget // features. switch (ARMProcFamily) { - case Cyclone: + case AppleA7: + case AppleA10: + case AppleA11: + case AppleA12: + case AppleA13: CacheLineSize = 64; PrefetchDistance = 280; MinPrefetchStride = 2048; diff --git llvm/lib/Target/AArch64/AArch64Subtarget.h llvm/lib/Target/AArch64/AArch64Subtarget.h index 5af4c0dd9c1..64095c8860f 100644 --- llvm/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -39,6 +39,11 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { public: enum ARMProcFamilyEnum : uint8_t { Others, + AppleA7, + AppleA10, + AppleA11, + AppleA12, + AppleA13, CortexA35, CortexA53, CortexA55, @@ -46,7 +51,6 @@ public: CortexA72, CortexA73, CortexA75, - Cyclone, ExynosM1, ExynosM3, Falkor, diff --git llvm/lib/Target/AArch64/AArch64SystemOperands.td llvm/lib/Target/AArch64/AArch64SystemOperands.td index dbc4deaf3f9..52c07f9b38c 100644 --- llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1328,5 +1328,5 @@ def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::ProcCyclone} }] in +let Requires = [{ {AArch64::ProcAppleA7} }] in def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;