From 3b28b6d0699762f1483514fa9535e44882ccc27d Mon Sep 17 00:00:00 2001 From: Sergey Fedorov Date: Sat, 22 Nov 2025 21:48:19 +0700 Subject: [PATCH 5/7] Add Armv8.5-A target Cherry-picks from https://github.com/llvm/llvm-project/commit/7c3c4baa3fbae3b4302a989000f5049b6db6c0e0 --- llvm/include/llvm/ADT/Triple.h | 1 + .../llvm/Support/AArch64TargetParser.def | 5 +++++ llvm/include/llvm/Support/ARMTargetParser.def | 5 +++++ llvm/lib/Support/TargetParser.cpp | 5 +++++ llvm/lib/Support/Triple.cpp | 2 ++ llvm/lib/Target/AArch64/AArch64.td | 3 +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 ++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 2 ++ .../AArch64/AsmParser/AArch64AsmParser.cpp | 2 ++ llvm/lib/Target/ARM/ARM.td | 17 +++++++++++++++++ llvm/lib/Target/ARM/ARMInstrInfo.td | 2 ++ llvm/lib/Target/ARM/ARMSubtarget.h | 3 +++ .../Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 1 + 13 files changed, 50 insertions(+) diff --git llvm/include/llvm/ADT/Triple.h llvm/include/llvm/ADT/Triple.h index c95b16dd4e8..2b0cbb798fe 100644 --- llvm/include/llvm/ADT/Triple.h +++ llvm/include/llvm/ADT/Triple.h @@ -101,6 +101,7 @@ public: enum SubArchType { NoSubArch, + ARMSubArch_v8_5a, ARMSubArch_v8_4a, ARMSubArch_v8_3a, ARMSubArch_v8_2a, diff --git llvm/include/llvm/Support/AArch64TargetParser.def llvm/include/llvm/Support/AArch64TargetParser.def index 8358acdca6b..b6d70e5a724 100644 --- llvm/include/llvm/Support/AArch64TargetParser.def +++ llvm/include/llvm/Support/AArch64TargetParser.def @@ -40,6 +40,11 @@ AARCH64_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "v8.4a", (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD)) +AARCH64_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "v8.5a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD)) #undef AARCH64_ARCH #ifndef AARCH64_ARCH_EXT_NAME diff --git llvm/include/llvm/Support/ARMTargetParser.def llvm/include/llvm/Support/ARMTargetParser.def index 78f5410fb73..26258165fa5 100644 --- llvm/include/llvm/Support/ARMTargetParser.def +++ llvm/include/llvm/Support/ARMTargetParser.def @@ -106,6 +106,11 @@ ARM_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "v8.4a", (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD)) +ARM_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "v8.5a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_DOTPROD)) ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, FK_NEON_FP_ARMV8, (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | diff --git llvm/lib/Support/TargetParser.cpp llvm/lib/Support/TargetParser.cpp index 2c167a4d086..ac97f1609e8 100644 --- llvm/lib/Support/TargetParser.cpp +++ llvm/lib/Support/TargetParser.cpp @@ -493,6 +493,8 @@ bool llvm::AArch64::getArchFeatures(AArch64::ArchKind AK, Features.push_back("+v8.3a"); if (AK == AArch64::ArchKind::ARMV8_4A) Features.push_back("+v8.4a"); + if (AK == AArch64::ArchKind::ARMV8_5A) + Features.push_back("+v8.5a"); return AK != AArch64::ArchKind::INVALID; } @@ -599,6 +601,7 @@ static StringRef getArchSynonym(StringRef Arch) { .Case("v8.2a", "v8.2-a") .Case("v8.3a", "v8.3-a") .Case("v8.4a", "v8.4-a") + .Case("v8.5a", "v8.5-a") .Case("v8r", "v8-r") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") @@ -767,6 +770,7 @@ ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) { case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: + case ARM::ArchKind::ARMV8_5A: return ARM::ProfileKind::A; case ARM::ArchKind::ARMV2: case ARM::ArchKind::ARMV2A: @@ -830,6 +834,7 @@ unsigned llvm::ARM::parseArchVersion(StringRef Arch) { case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: + case ARM::ArchKind::ARMV8_5A: case ARM::ArchKind::ARMV8R: case ARM::ArchKind::ARMV8MBaseline: case ARM::ArchKind::ARMV8MMainline: diff --git llvm/lib/Support/Triple.cpp llvm/lib/Support/Triple.cpp index b14d6492b1e..2321c0b9103 100644 --- llvm/lib/Support/Triple.cpp +++ llvm/lib/Support/Triple.cpp @@ -594,6 +594,8 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) { return Triple::ARMSubArch_v8_3a; case ARM::ArchKind::ARMV8_4A: return Triple::ARMSubArch_v8_4a; + case ARM::ArchKind::ARMV8_5A: + return Triple::ARMSubArch_v8_5a; case ARM::ArchKind::ARMV8R: return Triple::ARMSubArch_v8r; case ARM::ArchKind::ARMV8MBaseline: diff --git llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64.td index d02cfebab63..8df92103f70 100644 --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -212,6 +212,9 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; +def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", + "Support ARM v8.5a instructions", [HasV8_4aOps]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// diff --git llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/lib/Target/AArch64/AArch64InstrInfo.td index d6b8bb5d89c..f616276e109 100644 --- llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -22,6 +22,8 @@ def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; +def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, + AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, diff --git llvm/lib/Target/AArch64/AArch64Subtarget.h llvm/lib/Target/AArch64/AArch64Subtarget.h index 116096c3b00..fb272f1c466 100644 --- llvm/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -72,6 +72,7 @@ protected: bool HasV8_2aOps = false; bool HasV8_3aOps = false; bool HasV8_4aOps = false; + bool HasV8_5aOps = false; bool HasFPARMv8 = false; bool HasNEON = false; @@ -216,6 +217,7 @@ public: bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; } + bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; } diff --git llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 30a9a08f234..89281e7685a 100644 --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4927,6 +4927,7 @@ static void ExpandCryptoAEK(AArch64::ArchKind ArchKind, RequestedExtensions.push_back("aes"); break; case AArch64::ArchKind::ARMV8_4A: + case AArch64::ArchKind::ARMV8_5A: RequestedExtensions.push_back("sm4"); RequestedExtensions.push_back("sha3"); RequestedExtensions.push_back("sha2"); @@ -4945,6 +4946,7 @@ static void ExpandCryptoAEK(AArch64::ArchKind ArchKind, RequestedExtensions.push_back("noaes"); break; case AArch64::ArchKind::ARMV8_4A: + case AArch64::ArchKind::ARMV8_5A: RequestedExtensions.push_back("nosm4"); RequestedExtensions.push_back("nosha3"); RequestedExtensions.push_back("nosha2"); diff --git llvm/lib/Target/ARM/ARM.td llvm/lib/Target/ARM/ARM.td index 2e62a079041..13c40b60897 100644 --- llvm/lib/Target/ARM/ARM.td +++ llvm/lib/Target/ARM/ARM.td @@ -440,6 +440,9 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; +def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", + "Support ARM v8.5a instructions", [HasV8_4aOps]>; + //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // @@ -659,6 +662,20 @@ def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, FeatureRAS, FeatureDotProd]>; +def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; + def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, diff --git llvm/lib/Target/ARM/ARMInstrInfo.td llvm/lib/Target/ARM/ARMInstrInfo.td index d4c342cee5c..ae6e1ab142b 100644 --- llvm/lib/Target/ARM/ARMInstrInfo.td +++ llvm/lib/Target/ARM/ARMInstrInfo.td @@ -255,6 +255,8 @@ def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; +def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, + AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate<"FeatureVFP2", "VFP2">; diff --git llvm/lib/Target/ARM/ARMSubtarget.h llvm/lib/Target/ARM/ARMSubtarget.h index 74aee9a8ed3..2f3542ab643 100644 --- llvm/lib/Target/ARM/ARMSubtarget.h +++ llvm/lib/Target/ARM/ARMSubtarget.h @@ -106,6 +106,7 @@ protected: ARMv82a, ARMv83a, ARMv84a, + ARMv85a, ARMv8a, ARMv8mBaseline, ARMv8mMainline, @@ -153,6 +154,7 @@ protected: bool HasV8_2aOps = false; bool HasV8_3aOps = false; bool HasV8_4aOps = false; + bool HasV8_5aOps = false; bool HasV8MBaselineOps = false; bool HasV8MMainlineOps = false; @@ -529,6 +531,7 @@ public: bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; } + bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } diff --git llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 3373d691db5..3dc2ac39f9f 100644 --- llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -861,6 +861,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: + case ARM::ArchKind::ARMV8_5A: setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);